Manufacturing processors for Apple’s iPhone is prized business. The development of the Integrated Fan-Out (InFO) package has helped Taiwan Semiconductor Manufacturing Company (TSMC) manufacture the Apple A10 and A11 processors. Competitors such as Samsung have manufactured processors for Apple as recently as the generation before the introduction of InFO.
The InFO package is not a radically new design. InFO is a combination of processes that are known in the field. Fan-out wafer level processing (FOWLP), which InFO is based on, has been in use since embedded wafer-level ball-grid arrays in 2009. However, the InFO packaging combine FOWLP with redistribution layers, through layer vias, and package on package architecture to create a more efficient overall design.
FOWLP provides several advantages over other types of packaging. A fundamental problem of semiconductor manufacturing is that performance of integrated circuits increase as dimensions decrease but performance of interconnects often decrease with dimensional decrease. The dimensions of current integrated circuits create several problems for interconnections. The difficulty of manufacturing and resistance increase as dimensions decrease. Furthermore, the available area to connect inputs and outputs decreases. Therefore, as the performance of the integrated circuit increases, the number of inputs and outputs to connect the integrated circuit may decrease or remain stagnant. Crosstalk noise and shielding are also problematic as the space between the interconnects decreases.
FOWLP and InFO partially mitigate these problems by mounting the integrated circuit to a redistribution layer with efficient connections and more available space for inputs and outputs. In the figure below, the system on chip (SOC) is mounted to the redistribution layer. The figure depicts the area of the SOC compared to the greater area of the redistribution layer, shown in blue, which is used to mount input/outputs.
The InFO package provides performance benefits comparable to those seen in an iteration of scaling the dimensions of an integrated circuit. Specifically, TSMC has claimed a 20% reduction in overall package thickness, a 20% speed gain, and 10% better power dissipation. The reduction in overall package thickness is due to the elimination of a solder bump layer on the underside of the integrated circuit as discussed in the first blog post. The speed gain and power dissipation are due in part to efficient connections.
In TSMC’s paper InFO (Wafer Level Integrated Fan-Out) Technology, the benefits of InFO are discussed. The paper describes TSMC’s use of fine pitch connections in the redistribution layer with line width/space/ height of 2μm/2μm/2μm. TSMC was able to minimize the cross talk noise and increase shielding efficiency. The InFO package was tested and compared to a flip-chip package on package (FC-POP) method. FC-POP is used in many processors, including Apple’s previous generations. Compared to FC-POP, the InFO package showed 20% better eye-height opening, which is used to measure the integrity and noise of the signal. The InFO package also showed better power distribution performance. InFO had a 7 times lower impedance and reduced power noise by 47% compared to FC-POP. Further still, InFO showed better thermal performance. When both packages were supplied with the same power source, InFO showed a lower junction temperature, lower thermal resistance, and lower leakage current. The InFO package can therefore be operated at higher power without damaging materials. This information is shown below in a table provided in the paper.
A search of US patents assigned to TSMC, published since January 1, 2015, and including “Integrated fan-out” will populate 323 publications and 51 grants. Many of the publications include “Integrated fan-out” in the title. The applications range in claimed subject matter. The system itself is covered by many granted patents as well as methods of manufacture. Furthermore, specific structures such as polymer layers, connector pads, and shielding are also covered by granted patents. One example of an allowed claim is:
A method for forming a semiconductor package comprising: attaching a first die to a first carrier; depositing a first isolation material around the first die; after depositing the first isolation material, bonding a second die to the first die, wherein bonding the second die to the first die comprises forming a dielectric-to-dielectric bond; removing the first carrier; and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die, wherein the fan-out RDLs are electrically connected to the first die and the second die.
The example claim shows a reasonably broad scope considering the amount of art related to semiconductor packaging. The volume of the patent applications and grants, broad area of subject matter covered, and scope of the patents demonstrates TSMC’s investment in InFO and intellectual property to protect it. The portfolio may also provide a considerable advantage as competitors try to develop similar processes.
The next post will discuss how roles of companies surrounding electronics packaging are changing and the future of the market for fan-out packaging.
 InFO (Wafer Level Integrated Fan-Out) Technology Chien-Fu Tseng, Chung-Shi Liu, Chi-Hsi Wu, and Douglas Yu, 2016 IEEE 66th Electronic Components and Technology Conference
 Q3 2015 Taiwan Semiconductor Manufacturing Co Ltd Earnings Call http://www.tsmc.com/uploadfile/ir/quarterly/2015/3C2bO/E/TSMC%203Q15%20transcript.pdf